1. Field of the Invention
The present invention relates generally to a fabrication process for manufacturing semiconductor devices. More particularly, the present invention relates to a method and etchant for etching polysilicon.
2. Background
Polysilicon is widely used in semiconductor devices such as power transistors and deep trench capacitors. Power transistors are widely used in electrical systems requiring switches. For example, power transistors are found in numerous applications in the automotive industry. Deep trench capacitors are widely used in semiconductor device memory applications. In devices such as power transistors and deep trench capacitors, the polysilicon is subjected to a subtractive etch process known as xe2x80x9cetch-back.xe2x80x9d The etch-back process may be used to remove the material being etched (such as polysilicon) from a surface, leaving only the portion of the material which fills cavities beneath the surface, or may be used to remove only a portion of a material layer on a surface, leaving a horizontal layer of the material on the surface after etch-back.
xe2x80x9cDry etchingxe2x80x9d or xe2x80x9cplasma etchingxe2x80x9d involves exposing the material to be etched (polysilicon in this case) to a gaseous plasma. The plasma is typically created by RF excitation of a feed gas in a vacuum system, which generates reactive species from the feed gas, including species such as ions and other high energy species. These reactive species then react with and etch the polysilicon. xe2x80x9cReactive etchingxe2x80x9d relies primarily on diffusion to transport reactive species to the surface being etched, and is generally isotropic. Physical bombardment etching uses a voltage difference between the plasma and a substrate surface to accelerate charged species such as ions toward the substrate surface. Because of this acceleration, it is possible to achieve anisotropic etching. Reactive etching may be combined with physical bombardment etching.
When a sufficient voltage difference is used to drive charged species from the plasma toward a substrate, the etching proceeds at an appreciable rate in the direction of the acceleration of the charged species (normal to the substrate surface), while etching in lateral directions is minimal. This directionality is important in applications such as the etching of trench sidewalls perpendicular to the substrate surface. For a more detailed description of dry etch processes, see Runyan and Bean, Semiconductor Integrated Circuit Processing Technology, Ch. 6.3, pp. 269-280, 1990, which is incorporated herein by reference.
The chemical composition of an etchant plasma and the process conditions under which a substrate surface is exposed to chemically reactive species and/or physical bombardment by charged particles during dry etching can have significant effects on the properties of that surface.
Conventional feed gases used for plasma generation in the etch-back of polysilicon generally include at least one fluorine-containing gas. Inert gases such as argon (Ar), may also be included. Inert gases may be used as diluents, which facilitate control of the amount of reactive gas as well as other plasma properties. For anisotropic processes, inert gases may also be used to generate ions that contribute to anisotropic etching by bombarding the surface being etched. These non-reactive ions are unlikely to contribute to lateral etching, which is believed to be caused primarily by chemically reactive species. Chlorine gas (Cl2) may also be included. It is believed that the presence of chlorine improves the uniformity of the etch process.
However, it is very difficult to achieve a smooth polysilicon surface using etch-back with conventional feed gases. In particular, grains of polysilicon are often separated from a polysilicon layer, leaving holes/pits that result in a rough surface.
A power transistor is one example of a device that may incorporate etched-back polysilicon. FIG. 1 (prior art) shows a cross-sectional schematic of a typical power transistor 100 as it appears before and after a polysilicon xe2x80x9cetch-backxe2x80x9d process. Prior to etch-back, a trench 110 is present in an essentially single crystal silicon substrate 100. A gate oxide 120 covers the surfaces of silicon substrate 100, including the interior surfaces of trench 110. Typically,gate oxide 120 is silicon oxide. A polysilicon fill layer 140 both fills trench 110 and overlies the upper surface 125 of gate oxide layer 120. After etch-back, a portion 145 of polysilicon fill layer 140 is removed, so that a new polysilicon surface represented by, broken line 127 is formed. Back-etched polysilicon layer 130 remains, with surface 127 is slightly recessed into trench 110.
Another example of an application in which polysilicon etch-back is used is illustrated in FIG. 3 (prior art), which shows a cross-sectional schematic of a typical deep trench capacitor 300 as it appears before and after a polysilicon xe2x80x9cetch-backxe2x80x9d process. Prior to polysilicon etch-back, the device structure is as follows: A trench 303 is present in a silicon substrate 302. The silicon substrate 302 is essentially single crystal silicon, as opposed to polysilicon. A dielectric (typically silicon oxide) 306 covers the upper surface of silicon substrate 302. An etch barrier layer 308 (typically silicon nitride) overlies dielectric layer 306, followed by a conformal layer of silicon oxide 310 which covers the surface of etch barrier layer 308 and the interior surface 307 of trench 303 in silicon substrate 302. Finally, polysilicon fill layer 312 fills the trench and overlies the upper surface of silicon oxide conformal layer 310. After polysilicon etch back, the upper surface of the device structure is illustrated by broken line 314, where the upper surface of the etched-back polysilicon 316 is recessed into trench 303.
When conventional dry etch processes are used to etch-back the polysilicon, significant surface roughness is created on surface of the etched polysilicon, as described in detail below with reference to FIG. 2A.
FIG. 2A (prior art) shows a power transistor 200 similar to that shown in the FIG. 1 schematic, after portion 145 has been removed. In FIG. 2A, the etched surface of a polysilicon layer 227 has holes/pits 229 caused by the conventional etch-back process. These pits 229 may detrimentally affect the performance of a device, such as a power transistor, that incorporate polysilicon layer 227. In particular, the characteristics of materials deposited on the surface of polysilicon layer 227 may be adversely affected by the pits 229.
In accordance with the present invention, during a polysilicon etch back, a controlled amount of oxygen (O2) is added to the plasma generation feed gases, to reduce pitting of the etched back polysilicon surface. The plasma etchant is generated from a plasma source gas comprising: (i) at least one fluorine-containing gas, and (ii) oxygen.
The invention may be practiced in any of a number of apparatus adapted to expose polysilicon to a plasma etchant. One preferred apparatus is a decoupled plasma source (DPS(trademark), Applied Materials, Santa Clara, Calif.) etching system. Another preferred apparatus is a magnetically enhanced plasma (MXP(trademark), Applied Materials, Santa Clara, Calif.) etching system. Preferably, the invention is practiced in an apparatus having a memory that stores instructions for carrying out the process of the invention, a processor adapted to communicate with the memory and to execute the instructions stored by the memory, an etch chamber adapted to expose the substrate to the etchant in accordance with instructions from the processor, and a port adapted to pass communications between the processor and the etch chamber.